Dr. Bruno Allard, Professor and Head Manager at Ampere-Lab in Lyon, France, will present the SLC Seminar on Friday, March 18th. The seminar will be held in Min H. Kao, Room 525, from 12:10 to 1:20 pm.
Title: The two research paths of the ultimate integraton of power switch-mode coverters
Abstract: Ultimate integration of power switch-mode converter relies on two research paths. One path experiments the development of switched-capacitor converters. This approach fits silicon integration but is still limited in term of power density when targeted peak power is quite important. Inductive DC/DC architectures of converters suffer by the values and size of passive components. This limitation is addressed with an increase in switching frequency. Increase in switching losses in power switches leads to consider advanced technological nodes. Consequently, the capability with respect to input voltage is then limited.
Handling 3.3V input voltage to deliver an output voltage in the range 0.6V to 1.2V appears a challenging specification for an inductive buck converter if the smallest footprint is targeted at +90% efficiency.
Smallest footprint is approached through a 3D assembly of passive components to the active silicon die. High switching frequency is also considered to shrink the values of passive components as much as possible. From silicon integration point of view, it is well known that the proximity of decoupling capacitors to the power switches is mandatory for the sake of output voltage quality, efficiency, EMI and robustness.
In the context of on-chip power supply, the silicon technology is dictated by the payload, i.e. the digital functions. CMOS bulk C40 is selected as a study case for 3.3V input voltage. 3.3V LDMOSFET features poor QG.RDSon figure of merits and 1.2V standard core, regular devices are preferred. Moreover future integration as an on-chip power supply is more compatible. A 3-MOSFET cascode arrangement is experimented and confronted experimentally to a standard buck arrangement in the same technology. The coupled-phase architecture enables to reduce the switching frequency to half the operating frequency of the passive devices. +200MHz is selected for operation of passive devices.
CMOS bulk C40 offers MOM and MOS capacitors, in density too low to address the decoupling requirements. Capacitors have to be added externally to the silicon die but in a tight combination. Trench-cap technology is selected and capacitors are fabricated on a separate die that will act as an interposer to receive the silicon die as well as the inductors. The inductive devices must also be fabricated in an integrated manner to limit their footprint.
Bio: Dr. Bruno Allard received his M.S. and Ph.D. degrees in engineering from INSA Lyon, in France, in 1989 and 1992, respectively. He is a Full Professor at Ampere-Lab, in Lyon where he is currently the Head Manager. He has led numerous industrial and academic projects. He is the author or coauthor of more than 100 papers in Transactions and journals and 300 international conference contributions. His research interests include the integration of power systems, either hybrid or monolithic, power semiconductor device modeling and characterization, power electronic system design and low-power monolithic converter design.
Time: Friday, March 18, 12:20 PM - 1:10 PM EDT
Presenter: Dr. Bruno Allard, Head Manager at Ampere-Lab in Lyon, France
Location: Min Kao Building, Room 525
Steaming Information: Watch via WebEx
Meeting Number: 628 784 668
Meeting Password: power
Call-in Number: 1-650-479-3208 Access Code: 628 784 668